1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having a burst mode.
2. Description of the Related Art
Recently, in synchronous semiconductor memory devices such as synchronous DRAMs (SDRAMs), signals having phases in synchronism with the external clock signals are fed to plural data output circuits. Further, the SDRAM generally has a burst mode.
When a burst reading is interrupted by a write processing, a controller in the system receives a write command while interrupting the burst output. Specifically, in burst-reading the SDRAM, plural data are continuously output in synchronism with the clock signals, and when a write interrupt is received during the burst reading, the controller in the system receives a write command while interrupting the burst output of the SDRAM.
In the conventional semiconductor memory device, a data mask signal and a burst stop command are received in synchronism with the clock signals. Here, when the operation is interrupted by the write processing, a delay in interrupting the burst output data permits wasteful data to be output onto the data bus and, further, causes a delay in the timing for receiving a write command, resulting in a decrease in the efficiency for using the data bus.
The prior art and the problems associated with the prior art will be described in detail later with reference to accompanying drawings.
An object of the present invention is to provide a synchronous semiconductor memory device having a burst mode where an operation time is shortened when a burst reading is interrupted by a write processing, to enhance the efficiency for using the data bus, and to execute the operation at higher speeds.
According to the present invention, there is provided a semiconductor memory device having a function for interrupting a reading of data during a burst output in response to a data mask signal fed from an external unit, comprising a mask signal receiving circuit receiving the data mask signal out of synchronism and producing an asynchronous internal mask signal; wherein the reading of data during the burst output is interrupted by using the internal mask signal.
The semiconductor memory device may further comprise a data output circuit producing read data in synchronism with a clock signal, and an output control circuit producing an output control signal upon receiving the internal mask signal and masking the output data from the data output circuit. The mask signal receiving circuit may comprise a switch circuit interrupting a reception of the data mask signal for only a first period in synchronism with the clock signal; and a latch circuit holding a state of before being interrupted; wherein the data output circuit may mask the output data upon receiving the output control signal during the first period.
The first period may be set to a delay time shorter than a time for holding the data mask signal for the clock signal. The mask signal receiving circuit may have a first operation mode and a second operation mode, the first operation mode being a mode for receiving the data mask signal out of synchronism, and the second operation mode being a mode for receiving the data mask signal in synchronism with the clock signal.
The semiconductor memory device may further comprise a register in which the first operation mode and the second operation mode are set. An operation mode of the mask signal receiving circuit may be generated based upon a latency data set to the register. The data output circuit may produce an output of a high-impedance state in response to the output control signal, and may mask the output data.